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ARGO

Title
WCET-Aware Parallelization of Model-Based Applications for Heterogeneous Parallel Systems
Funding
EC | H2020 | RIA
Call
H2020-ICT-2015
Contract (GA) number
688131
Start Date
2016/01/01
End Date
2019/03/31
Open Access mandate
yes
Data Pilot
no
Organizations
ABSINT, UR1, RS, SCILAB, Fraunhofer, KIT, DLR, EMX, TWG
More information
Detailed project information (CORDIS)

 

  • WCET-aware parallelization of model-based applications for multi-cores: The ARGO approach

    Derrien, Steven; Puaut, Isabelle; Alefragis, Panayiotis; Bednara, Marcus; Bucher, Harald; David, Clement; Debray, Yann; Durak, Umut; Fassi, Imen; Ferdinand, Christian; Hardy, Damien; Kritikakou, Angeliki; Rauwerda, Gerard; Reder, Simon; Sicks, Martin;... (2017)
    Projects: EC | ARGO (688131)
    International audience; Parallel architectures are nowadays not only confined to the domain of high performance computing, they are also increasingly used in embedded time-critical systems. The ARGO H2020 project 1 provides a programming paradigm and associated tool flow to exploit the full potential of architectures in terms of development productivity, time-to-market, exploitation of the platform computing power and guaranteed real-time performance. In this paper we give an overview of the ...

    DYNASCORE: DYNAmic Software COntroller to increase REsource utilization in mixed-critical systems

    Kritikakou , Angeliki; Marty , Thibaut; Roy , Matthieu (2018)
    Projects: EC | ARGO (688131)
    International audience; In real-time mixed-critical systems, Worst-Case Execution Time analysis (WCET) is required to guarantee that timing constraints are respected —at least for high criticality tasks. However, the WCET is pessimistic compared to the real execution time, especially for multicore platforms. As WCET computation considers the worst-case scenario, it means that whenever a high criticality task accesses a shared resource in multi-core platforms, it is considered that all cores u...

    Using Polyhedral Techniques to Tighten WCET Estimates of Optimized Code: A Case Study with Array Contraction

    Lefeuvre , Thomas; Kasnakli , Emin ,; Fassi , Imen; Puaut , Isabelle; Cullmann , Christoph; Derrien , Steven; Gebhard , Gernot (2018)
    Projects: EC | ARGO (688131)
    International audience; The ARGO H2020 European project aims at developing a Worst-Case Execution Time (WCET)-aware parallelizing compilation toolchain. This toolchain operates on Scilab and XCoS inputs, and targets ScratchPad memory (SPM)-based multi-cores. Data-layout and loop transformations play a key role in this flow as they improve SPM efficiency and reduce the number of accesses to shared main memory. In this paper, we study how these transformations impact WCET estimates of sequentia...

    Tightening Contention Delays While Scheduling Parallel Applications on Multi-core Architectures

    Rouxel , Benjamin; Derrien , Steven; Puaut , Isabelle (2017)
    Projects: EC | ARGO (688131)
    International audience; Multi-core systems are increasingly interesting candidates for executing parallel real-time applications, in avionic, space or automotive industries, as they provide both computing capabilities and power efficiency. However, ensuring that timing constraints are met on such platforms is challenging, because some hardware resources are shared between cores. Assuming worst-case contentions when analyzing the schedulability of applications may result in systems mistakenly ...

    Cache Partitioning + Loop Tiling: A Methodology for Effective Shared Cache Management

    Kelefouras, Vasilios; Keramidas, Georgios; Voros, Nikolaos (2017)
    Projects: EC | ARGO (688131)
    In this paper, we present a new methodology that provides i) a theoretical analysis of the two most commonly used approaches for effective shared cache management (i.e., cache partitioning and loop tiling) and ii) a unified framework to fine tuning those two mechanisms in tandem (not separately). Our approach manages to lower the number of main memory accesses by one order of magnitude keeping at the same time the number of arithmetical/addressing instructions in a minimal level. We also pres...

    A hybrid approach for mapping and scheduling on heterogeneous multicore systems

    Emeretlis, A.; Theodoridis, G.; Alefragis, P.; Voros, N. (2016)
    Projects: EC | ARGO (688131)

    Combining software cache partitioning and loop tiling for effective shared cache management

    Kelefouras, Vasileios; Keramidas, Georgios; Voros, Nikolaos
    Projects: EC | ARGO (688131)
    One of the biggest challenges in multicore platforms is shared cache management, especially for data dominant\ud applications. Two commonly used approaches for increasing shared cache utilization are cache partitioning\ud and loop tiling. However, state-of-the-art compilers lack of efficient cache partitioning and loop tiling\ud methods for two reasons. First, cache partitioning and loop tiling are strongly coupled together, thus addressing\ud them separately is simply not effective. Second, ...
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