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Sharma, Saurabh; Maheshwari, Sanjeev; Kumar, Sanjeev; Vrince, Vimal (2013)
Publisher: Journal of Engineering Computers & Applied Sciences
Journal: Journal of Engineering Computers & Applied Sciences
Languages: English
Types: Article
Subjects: Engineering; Electronics and Communication Engineering, NMOS, PMOS. CMOS, domino logic, weaker PMOS Tool Used---- Tanner

Classified by OpenAIRE into

ACM Ref: Hardware_PERFORMANCEANDRELIABILITY, Hardware_INTEGRATEDCIRCUITS, Hardware_GENERAL
A technology is proposed in this literature to simultaneously reduce the charge sharing problem in the dynamiccircuits due to the generation of the parasitic capacitor at each node. Here we used a weak PMOS pull-up device(with a small W/L ratio) to the dynamic CMOS stage output to reduce the effect of the parasitic capacitor
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