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Anders, J.; Mathis, W.; Ortmanns, M. (2007)
Languages: English
Types: Article
Subjects:
Im vorliegenden Artikel wird eine vollstängige, d.h. unter Einbeziehung des Eingangssignals, Äquivalenz zwischen zeitkontinuierlichen und zeitdiskreten ΣΔ-Modulatoren im Zustandsraum hergeleitet. Es wird ebenfalls gezeigt, wie eine wichtige Nichtidealität, das sog. "excess loop delay", in den Berechnungen berücksichtigt werden kann. Die dargestellte Methode dient dazu, den Entwurf und dabei vor allem die Stabilitätsuntersuchungen, von zeitkontinuierlichen ΣΔs auf die bereits empirisch intensiv erforschten zeitdiskreten Systeme zurückzuführen.

In the article at hand a complete equivalency, i.e. including the input signal, between continuous-time and discrete-time ΣΔ-modulators in state-space is derived. In addition, it is shown, how one can incorporate the important non-ideality of "excess loop delay" into the formalism. The method introduced is supposed to facilitate the design, especially the stability analysis part of the design, of continuous-time ΣΔs by making use of the empirically thoroughly examined discrete-time systems.

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