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fbtwitterlinkedinvimeoflicker grey 14rssslideshare1
Opoku Agyeman, Michael; Zong, Wen (2017)
Publisher: IEEE
Languages: English
Types: Other
Subjects: TK5103.2

Classified by OpenAIRE into

ACM Ref: Hardware_INTEGRATEDCIRCUITS
To meet the performance and scalability demands of the fast-paced technological growth towards exascale and Big-Data processing with the performance bottleneck of conventional metal based interconnects, alternative interconnect fabrics such as inhomogeneous three dimensional integrated Network-on-Chip (3D NoC) has emanated as a cost-effective solution for emerging multi-core design. However, these interconnects trade-off optimized performance for cost by restricting the number of area and power hungry 3D routers. Consequently, in this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to alleviate the performance degradation due to the slow 2D routers in inhomogeneous 3D NoCs. By combining the low-complexity bypassing technique with adaptive routing, the proposed router is able to balance the traffic in the network to reduce the average packet latency under various traffic loads. Simulation shows that, the proposed router can reduce the average packet delay by an average of 45% in 3D NoCs.
  • The results below are discovered through our pilot algorithms. Let us know how we are doing!

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  • Discovered through pilot similarity algorithms. Send us your feedback.

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