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Axelos, N.; Watson, J.; Taylor, D.; Platts, A. (2002)
Languages: English
Types: Article
Subjects: TK, QA75

Classified by OpenAIRE into

Transient Response Testing has been shown to be a very powerful and economical functional test technique for linear analogue cells in mixed-signal systems. Recently this work has been extended to non-linear analogue circuits by treating Transient Response Testing as a structural test technique and employing optimised and reduced fault sets that are derived from Inductive Fault Analysis and circuit sensitivity analyses. These developments have been very successful and have also facilitated a novel BIST methodology for analogue circuits. The BIST scheme employs a generic on-chip stimulus for all analogue cells and features a specially designed test cell that coordinates a short test sequence that involves sampling the transient response at key instants in the test cycle and comparing to a known reference.
  • The results below are discovered through our pilot algorithms. Let us know how we are doing!

    • 1. P. S. A. Evans, M. Al Qutayri, P. R. Shepherd, “A Novel Technique for Testing Mixed-Signal ICs”,Proceedings of ITC, 1991, pp301-306
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    • 3. I. C. Butler, D.Taylor, and T.I.Pritchard: 'Effects of Response Quantisation on the Accuracy of Transient Response Test Results', IEE Proceedings Circuits Devices Systems., 1995, 142, (5), pp 334-338
    • 4. R. J. Binns, D. Taylor, T. I. Pritchard, "Testing Linear Macros in Mixed-Signal Systems using Transient Response Testing and Dynamic Supply Current Monitoring" IEE Electronics Letters, No.30, Vol. 15 , 21st July 1994, pp 1216-1217
    • 5. R. J. Binns, D. Taylor, T. I. Pritchard, “Generating, Capturing and Processing Supply Current Signatures from Analogue Macros in Mixed-Signal Systems”, The Microlectronics Journal, Vol. 27, 1996.
    • 6. IEEE Standard 1149.1: “Standard Test Access Port and Boundary Scan Architecture”, The Computer Society, IEEE, 1990
    • 7. M. Sachdev, “A defect oriented testability methodology for analog circuits,” Journal of Electronic Testing: Theory and Applications, vol. 6, no. 3, 1995, pp. 265-276.
    • 8. T. Olbrich, J. Perez, I. A. Grout, A.M. Richardson, and C. Ferrer, "Defect-oriented vs Schematic-Level based fault Simulation for Mixed-Signal ICs." IEEE International Test Conference, 1996, pp.511-521.
    • 10. A. Milne, D. Taylor, K. Naylor, “Assessing and Comparing Fault Coverage When Testing Analogue Circuits”, IEE Proceedings Circuits Devices and Systems, Vol. 144, No. 1, 1997, pp1-4.
    • 11. A. Platts, D. Taylor, “Transient Response Testing of NonLinear Analogue Circuits Using Optimised Fault Sets, Submitted to IEE Proceeding Circuits Devices and Systems.
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