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Publisher: Department of Automatic Control and Systems Engineering
Languages: English
Types: Book
Subjects:

Classified by OpenAIRE into

arxiv: Computer Science::Hardware Architecture
This paper presents an investigation into the development of performance metrics for sequential and parallel architectures. Speedup and efficiency are defined using the concept of virtual processor. These are utilised to obtain the best task allocation to processors in parallel architectures achieving maximum efficiency and speedup. The performance metrics developed are general and applicable to both heterogeneous and homogeneous architectures and ensure that capabilities of the processors are exploited by maximising the efficiency of the architecture. The proposed concepts are validated experimentally using several algorithms and architectures including digital signal processing and message-passing systems.
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