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Publisher: Institute of Electrical and Electronics Engineers
Languages: English
Types: Unknown
Subjects:

Classified by OpenAIRE into

ACM Ref: Hardware_INTEGRATEDCIRCUITS
Flip Chip (FC) technology offers many advantages over conventional surface mount technology, including a smaller device footprint and higher interconnection density. Low power but complex consumer items, such as mobile telecommunications devices, utilise this packaging technology and it is likely to spread to other electronics sectors where components have higher power dissipations and/or they have to operate in a hostile environment. As the scope for FC packaging broadens, a reliable means of establishing the long term performance of a particular package is necessary. Traditionally thermal cycling has been a primary reliability test for electronic assemblies including FC, however this fails to capture the behaviour of assemblies where the component thermal expansion is well matched to that of the substrate due to the isothermal heating and cooling of the assembly. In this situation power cycling offers an alternative means of determining the module performance. This paper describes the use of Finite Element Modeling (FEM) to explore the effects of power cycling on a silicon on silicon Multi-Chip Module (MCM) constructed with a low solder joint standoff height of 30-35µm. Particular attention was given to the boundary conditions that are inevitably atypical of those used in traditional thermal cycling. The paper presents results of the temperature distributions throughout the assembly, which were found to depend upon the substrate base material (FR4 or copper) that the MCM was attached to. The results of the FEM analysis were verified by assembling test devices and measuring their temperature distribution under steady state and power cycling conditions. The predicted temperatures may then be used as boundary conditions in FEM of thermal stresses and fatigue in the assembly.
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    • It was found that while the temperature difference between the heater and the carrier chips were shown to be very similar regardless of the substrate, the MCMs on copper substrates reached a much lower peak temperature than those on FR4 for a given power level.
    • [1] J.H. Lau (ed), Low Cost Flip Chip Technologies, (Chapter 1), McGraw-Hill, New York, 1999.
    • [2] G. Grossmann and L. Weber “Metallurgical Considerations for Accelerated Testing of Soft Solder Joints” IEEE Trans. Comp. Pack. and Man. Tech. Part C Volume 20 No 3, July 1997, pp 213-8.
    • [3] J. H. Pang, et al, “Thermal Cycling Aging Effects on Microstructual and Mechanical Properties of a Single PBGA Solder Joint Specimen” IEEE Trans. Comp. Pack. Tech. Volume 24 No 1, March 2001, pp 10-15.
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    • [5] P. Towashiraporn, et al, “Predictive Reliability Models through Validated Correlation between Power Cycling and Thermal Cycling Accelerated Life Tests” Soldering and Surface Mount Technology, Vol, 14 Issue 3, 2002, pp 51-60.
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    • [8] D. A. Hutt, et al, “A Maskless Low-Cost Multi-Chip Module Assembly Process” Advances in Electronic Packaging (Proceedings of the InterPACK99 conference) Hawaii, ASME EEP Volume 26-2, 1999, pages 1705-11.
    • [9] F. Sarvar, et al , “IGBT Package Design for High Power Aircraft Electronic Systems” Journal of Electronic Packaging ASME, Vol 123 No. 4, 2001, pp 338-43
    • [10] F. Sarvar et al., “PCB glass-fibre Laminates: Thermal Conductivity Measurements and their effect on simulation” AIME Journal of Electronic Materials, Vol. 19 No 20, 1990, pp 1345-50
    • [11] K.D. Hagen, Heat transfer with applications, Prentice Hall, London, 1998
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