Remember Me
Or use your Academic/Social account:


Or use your Academic/Social account:


You have just completed your registration at OpenAire.

Before you can login to the site, you will need to activate your account. An e-mail will be sent to you with the proper instructions.


Please note that this site is currently undergoing Beta testing.
Any new content you create is not guaranteed to be present to the final version of the site upon release.

Thank you for your patience,
OpenAire Dev Team.

Close This Message


Verify Password:
Verify E-mail:
*All Fields Are Required.
Please Verify You Are Human:
fbtwitterlinkedinvimeoflicker grey 14rssslideshare1
Duan, Meng; Zhang, Jian Fu; Ji, Zhigang; Zhang, Wei Dong; Vigar, David; Asenov, Asen; Gerrer, Louis; Chandra, Vikas; Aitken, Rob; Kaczer, Ben (2016)
Publisher: Institute of Electrical and Electronics Engineers
Languages: English
Types: Article
Subjects: TK
The access transistor of SRAM can suffer both Positive Bias Temperature Instability (PBTI) and Hot Carrier Aging (HCA) during operation. The understanding of electron traps (ETs) is still incomplete and there is little information on their similarity and differences under these two stress modes. The key objective of this paper is to investigate ETs in terms of energy distribution, charging and discharging properties, and generation. We found that both PBTI and HCA can charge ETs which center at 1.4eV below conduction band (Ec) of high-k (HK) dielectric, agreeing with theoretical calculation. For the first time, clear evidences are presented that HCA generates new ETs, which do not exist when stressed by PBTI. When charged, the generated ETs’ peak is 0.2eV deeper than that of pre-existing ETs. In contrast with the power law kinetics for charging the pre-existing ETs, filling the generated ETs saturates in seconds, even under an operation bias of 0.9 V. ET generation shortens device lifetime and must be included in modelling HCA. A cyclic and anti-neutralization ETs model (CAM) is proposed to explain PBTI and HCA degradation, which consists of pre-existing cyclic electron traps (PCET), generated cyclic electron traps (GCET), and anti-neutralization electron traps (ANET).
  • The results below are discovered through our pilot algorithms. Let us know how we are doing!

    • [1] E. Cartier, B. P. Linder, V. Narayanan, and V. K. Paruchuri, “Fundamental understanding and optimization of PBTI in nFETs with SiO2/HfO2 gate stack,” in IEDM Tech. Dig., 2006, pp. 57-60.
    • [2]S. Ramey, A. Ashutosh, C. Auth, J. Clifford, M. Hattendorf, J. Hicks, “Intrinsic transistor reliability improvements from 22 nm tri-gate technology”, in Proc. IEEE IRPS, Apr. 2013, pp. 4C.5.1-4C.5.5.
    • [3] S. Pae, M. Agostinelli, M. Brazier, R. Chau, G. Dewey, T. Ghani, M.
    • Thomas, C. Wiegand, and J. Wiedemer, “BTI Reliability of 45nm high-k Metal-Gate Process Technology”, IRPS 2008, pp352-357.
    • [4] M. Duan, J. F. Zhang, Z. Ji, W. Zhang, B. Kaczer, T. Schram, R.
    • 61, no. 9, Sep. 2014.
    • [5] J. F. Zhang, “Defects and instabilities in Hf-dielectric/SiON stacks (Invited Paper),” Microelectro. Eng., vol. 86, no.7-9, pp.1883-1887, 2009.
    • [6] S. Zafar, A. Callegari, E. Gusev, and M. V. Fischetti, “Charge trapping in high-κ gate dielectric stacks”, in IEDM Tech. Dig., 2002, pp. 517-520.
    • [7] E. Cartier, A. Kerber, “Stress-Induced Leakage Current and Trap Generation in nFETs with HfO2/TiN Gate Stacks during Positive-Bias Temperature Stress”, Int. Reliab. Phys. Symp. (IRPS) Proc., p. 486, 2009.
    • [8] X. F. Zheng, W. D. Zhang, B. Govoreanu, D. R. Aguado, J. F. Zhang, and J.
    • Van Houdt, “Energy and Spatial Distributions of Electron Traps Throughout SiO2/Al2O3 Stacks as the IPD in Flash Memory Application,” IEEE Trans.
    • Electron Devices, vol. 57, no. 1, pp. 288, 2010.
    • [9] E. H. Nicollian, C. N. Berglund, P. F. Schmidt, and J. M. Andrews, “Electrochemical charging of thermal SiO2 films by injected electron currents,”, J. Appl. Phys., vol. 42, no. 13, pp. 5654-5664, 1971.
    • [10] J. F. Zhang, S. Taylor, W. Eccleston, “A Quantitative Invetiagtion of Electron Detrapping in SiO2 under Fowler-Nordheim Stress”. Journal of Applied Physics vol. 71 issue 12, pp.5989-5996, Jun. 15 1992 [11] J. F. Zhang, C. Z. Zhao, M. B. Zahid, G. Groeseneken, R. Degraeve, and S.
    • De Gendt, “An assessment of the location of as-grown electron traps in HfO2/HiSiO stacks,”IEEE Elec. Device Lett.,vol.27, no.10, pp.817-820, 2006.
    • [12] C. Z. Zhao, J. F. Zhang, M. B. Zahid, B. Govoreanu, G. Groeseneken, and S. De Gendt, “Determination of capture cross sections for as-grown electron traps in HfO2/HfSiO stacks,” J. Appl. Phys., vol. 100, no. 9, p. 093 716, 2006.
    • [13] K. T. Lee, C. Y. Kang, O. S. Yoo, R. Choi, B. H. Lee, J. C. Lee, H. D. Lee, and Y. H. Jeong, “PBTI-Associated High-Temperature Hot Carrier Degradation of nMOSFETs With Metal-Gate/High-k Dielectrics”, IEEE Trans.
    • Electron Devices, vol. 29, no. 4, pp. 389-391, April 2008.
    • [14] M. Duan, J. F. Zhang, A. Manut, Z. Ji, W. Zhang, A. Asenov, L. Gerrer, D.
    • Groeseneken, “Hot carrier aging and its variation under use-bias: kinetics, prediction, impact on Vdd and SRAM”, International Electron Devices Meeting (IEDM), pp. 547-550, Washington DC, Dec. 7-9, 2015.
    • [15] A. Bravaix1, Y. M. Randriamihaja, V. Huard, D. Angot, X. Federspiel, W.
    • Arfaoui, P. Mora, F. Cacho, M. Saliva,C. Besset, S. Renard, D. Roy, E. Vincent, “Impact of the gate-stack change from 40nm node SiON to 28nm High-K Metal Gate on the Hot-Carrier and Bias Temperature damage”, IRPS 2013,pp 2D.6.1-2D.6.9.
    • [16] M. Cho, P. Roussel, B. Kaczer, R. Degraeve, J. Franco, M. Aoulaiche, T.
    • Chiarella, T. Kauerauf, N. Horiguchi, and G. Groeseneken, “Channel Hot Carrier Degradation Mechanism in Long/Short Channel n-FinFETs”, IEEE Trans. Electron Devices, vol. 60, no. 12, Dec. 2013 [17] S. E. Rauch and G. La Rosa, “The energy-driven paradigm of NMOSFET Hot-carrier effects,” IEEE Trans. Device Mater. Rel., vol. 5, no. 4, pp. 701-705, Dec. 2005.
    • [18] X. F. Zheng, W. D. Zhang, B. Govoreanu, J. F. Zhang, J. van Houdt, “A discharge-based multi-pulse technique (DMP) for probing electron trap energy distribution in high-k materials for Flash memory application”, International Electron Devices Meeting (IEDM), 2009, pp139-142.
    • [19] S. F. W. M. Hatta, Z. Ji, J. F. Zhang, M. Duan, W. Zhang, N. Soin, B.
    • Kaczer, S. De Gendt, and G. Groeseneken, “Energy distribution of positive charges in gate dielectric: probing technique and impacts of different defects”, IEEE Trans. Electron Dev., Vol. 60, No. 5, pp. 1745-1753, 2013.
    • [20] J. Ma, J. F. Zhang, Z. Ji, B. Benbakhti, W. Zhang, J. Mitard, B. Kaczer, G.
    • Groeseneken, S. Hall, J. Robertson, and P. Chalker, “Energy Distribution of Positive Charges in Al2O3/GeO2/Ge pMOSFETs”, IEEE Elec. Dev. Lett., Vol.
    • 35, No. 2, pp.162-164, 2014.
    • [21]J. Robertson, “High dielectric constant gate oxides for metal oxide Si transistors,” Rep. Prog. Phys., Vol.69, pp. 327-396, 2006.
    • [22] M. Duan, J. F. Zhang, Z. Ji, W. Zhang, B. Kaczer, S. De Gendt, and G.
    • Groeseneken, “New insights into defect loss, slowdown, and device lifetime enhancement,” IEEE Trans. Electron Dev., Vol. 60, No. 1, pp. 413-419, 2013.
    • [23] T. Grasser, Th. Aichinger, G. Pobegen, H. Reisinger,P.-J. Wagner, J.
    • Franco, M. Nelhiebel, and B. Kaczer, “The 'Permanent' Component of NBTI: Composition and Annealing”. IRPS 2011, p. 605-613.
    • [24] V. Huard, “Two independent components modeling for negative bias temperature instability,” in Proc IEEE IRPS, 2010, pp. 33-42.
    • [25] D.S.Ang, G.A.Du, Y.Z.Hu, S.Wang, C.M.Ng, “Energy distribution and electrical characteristics of NBTI induced Si/SiON inerface states”, IRPS 2008,pp 737-738.
    • [26] N. H. Hsu, J. W. You, H. C. Ma, S. C. Lee, E. Chen, L. S. Huang, Y. C.
    • Cheng, O. Cheng, I. C. Chen, “Intrinsic Hot-Carrier Degradation of nMOSFETs by Decoupling PBTI Component in 28nm High-K/Metal Gate Stacks”, IRPS 2012, pp XT.13.1-XT.13.4.
    • [27] J. Ma, J. F. Zhang, Z. Ji, B. Benbakhti, W. D. Zhang, X. F. Zheng, J.
    • Mitard, B. Kaczer, G. Groeseneken, S. Hall, J. Robertson, and P. R. Chalker, “Characterization of Negative-Bias Temperature Instability of Ge MOSFETs With GeO2/Al2O3 Stack,” IEEE Trans. Electron Dev., Vol. 61, No. 5, pp.
    • [28] M. H. Chang, J. F. Zhang, and W. Zhang, “Assessment of Capture Cross Sections and Effective Density of Electron Traps Generated in Silicon Dioxides”, IEEE Trans. Electron Devices, vol. 53, no. 6, pp. 1347-1354, 2006.
  • No related research data.
  • No similar publications.

Share - Bookmark

Cite this article