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Wang, Xingsheng; Cheng, Binjie; Reid, David; Pender, Andrew; Asenov, Plamen; Millar, Campbell; Asenov, Asen (2015)
Publisher: Institute of Electrical and Electronics Engineers
Languages: English
Types: Article

Classified by OpenAIRE into

In this paper, we present a FinFET-focused variability-aware compact model (CM) extraction and generation technology supporting design-technology co-optimization. The 14-nm CMOS technology generation silicon on insulator FinFETs are used as testbed transistors to illustrate our approach. The TCAD simulations include a long-range process-induced variability using a design of experiment approach and short-range purely statistical variability (mismatch). The CM extraction supports a hierarchical CM approach, including nominal CM extraction, response surface CM extraction, and statistical CM extraction. The accurate CM generation technology captures the often non-Gaussian distributions of the key transistor figures of merit and their correlations preserving also the correlations between process and statistical variability. The use of the hierarchical CM is illustrated in the simulation of FinFET-based SRAM cells and ring oscillators.
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    • [1] C. Auth, C. Allen, A. Blattner, et al., “A 22nm High Performance and Low-Power CMOS Technology Featuring Fully-Depleted Tri-Gate Transistors, Self-Aligned Contacts and High Density MIM Capacitors,” in Proc. Symp. VLSI Tech. Dig., 2012, pp.131-132.
    • [2] N. Planes, O. Weber, V. Barral, et al., “28 nm FDSOI technology platform for high-speed low-voltage digital applications,” in Proc. Symp. VLSI Technol., Jun. 2012, pp. 133-134.
    • [3] In E. Karl, Z. Guo, Y.-G. Ng, J. Keane, U. Bhattacharya, K. Zhang, “The impact of assist-circuit design for 22nm SRAM and beyond,” in Proc. IEEE IEDM, 2012, pp.561-564.
    • [4] B. Nikolic, J.-H. Park, J. Kwak, et al., “Technology variability from a design perspective,” IEEE Trans. Circuits and systems-I: regular papers, vol.58 no.9, pp.1996-2009, Sept. 2011.
    • [5] A. Asenov, “Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 µm MOSFETs: A 3D “atomistic” simulation study,” IEEE Trans. Electron Dev. Vol. 45, No. 12, pp. 2505-2513, 1998.
    • [6] H. F. Dadgour, K. Endo, V. K. De, K. Banerjee, “Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors-Part I: Modeling, Analysis, and Experimental Validation,” IEEE Trans. Elec. Dev., vol.57 no.10, pp.2504-2514, Oct. 2010.
    • [7] X. Wang, A. R. Brown, N. M. Idris, S. Markov, G. Roy and A. Asenov, “Statistical Threshold-Voltage Variability in Scaled Decananometer Bulk HKMG MOSFETs: A Full-Scale 3-D Simulation Scaling Study,” IEEE Trans. on Electron Devices, Vol. 58, No. 8, pp. 2293-2301, Aug. 2011.
    • [8] T. Matsukawa, Y. Liu, W. Mizubayashi, et al., “Suppressing Vt and Gm variability of FinFETs using amorphous metal gates for 14nm and beyond,” in Proc. IEDM, 2012, pp.8.2.1-8.2.4
    • [9] A. Asenov, S. Kaya and A. R. Brown, “Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness,” IEEE Trans. on Electron Devices, Vol. 50, No. 5, pp. 1254-1260, 2003.
    • [10] X. Wang, B. Cheng, A. R. Brown, C. Millar, J. B. Kuang, S. Nassif, and A. Asenov, “Interplay between process-induced and statistical variability in 14-nm CMOS technology double-gate SOI FinFETs,” IEEE Trans. on Electron Devices, Vol.60 No.8, pp.2485-2492, August 2013.
    • [11] S. Nassif, “Design for variability in DSM technologies,” in Proc. ISQED, 2000, pp.451-454.
    • [12] T. Austin, V. Bertacco, D. Blaauw, and T. Mudge, “Opportunities and Challenges for better than worst-case design,” in Proc. ASP-DAC, 2005, pp.I-1-7.
    • [13] S.-Y. Wu, C. Y. Lin, M. C. Chiang, et al., “An Enhanced 16nm CMOS Technology Featuring 2nd Generation FinFET Transistors and Advanced Cu/Low-k Interconnect for Low Power and High Performance Applications,” in Proc. IEEE IEDM, 2014, pp.3.1.1-3.1.4.
    • [14] S. Natarajan, M. Agostinelli, S. Akbar, et al., “A 14nm Logic Technology Featuring 2nd-Generation FinFET transistors, Air-Gapped Interconnects, Self-Aligned Double Patterning and a 0.0588 m2 SRAM cell size,” in Proc. IEEE IEDM, 2014, pp.3.7.1-3.7.4.
    • [15] C.-H. Lin, B. Greene, S. Narasimha, et al., “High Performance 14nm SOI FinFET CMOS Technology with 0.0174µm2 embedded DRAM and 15 Levels of Cu Metallization,” in Proc. IEEE IEDM, 2014, pp.3.8.1-3.8.4.
    • [16] A. Asenov, B. Cheng, X. Wang, A.R. Brown, D. Reid, C. Millar, C. Alexander, “Simulation based transistor-SRAM co-design in the presence of statistical variability and reliability,” in Proc. IEEE IEDM, 2013, pp.818-821.
    • [17] S. Yang, L. Ge, J. Lin, et al., “High Performance Mobile SoC Design and Technology Co-Optimization to Mitigate High-K Metal Gate Process Induced Variations,” in Symp. VLSI Tech. Dig., 2014, pp.1-2.
    • [18] X. Jiang, et al., “New Assessment Methodology Based on Energy-Delay-Yield Co-Optimization for Nanoscale CMOS Technology,” IEEE Trans. Elec. Dev., vol.62 no.6, pp.1746-1753, 2015.
    • [19] A. Asenov, et al., “Variability aware simulation based design-technology co-optimization (DTCO) flow in 14 nm FinFET/SRAM co-optimization,” IEEE Transactions on Electron Devices, Vol. 62 No. 6, pp.1682-1690, June 2015.
    • [20] The GSS tool chain. [online] http://www.goldstandardsimulations.com/products/
    • [21] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching properties of MOS transistors,” IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433-1439, Oct. 1989.
    • [22] BSIM-CMG 106, [online] http://www-device.eecs.berkeley.edu/bsim/?page=BSIMCMG
    • [23] K. Takeuchi and M. Hane, “Statistical compact mode parameter extraction by direct fitting to variations,” IEEE Trans. Elec. Dev., vol.55 no.6, pp.1487-1493. June 2008.
    • [24] B. Cheng, D. Dideban, N. Moezi, C. Millar, G. Roy, X. Wang, S. Roy and A. Asenov, “Statistical Variability Compact Modeling Strategies for BSIM4 and PSP,” IEEE Design and Test of Computers, Vol. 27, No. 2, pp. 26-35, Mar./Apr. 2010.
    • [25] X. Wang, B. Cheng, A. R. Brown, C. Millar, C. L. Alexander, D. Reid, J. B. Kuang, S. Nassif and A. Asenov, “Unified Compact Modelling Strategies for Process and Statistical Variability in 14-nm node DG FinFETs,” in Proc. 18th International Conference on Simulation of Semiconductor Processes and Devices, 2013, pp. 139-142.
    • [26] U. Kovac, D. Dideban, B. Cheng, N. Moezi, G. Roy and A. Asenov, "A Novel Approach to the Statistical Generation of Non-normal Distributed PSP Compact Model Parameters using a Nonlinear Power Method," in Proc. Simulation of Semiconductor Processes and Devices (SISPAD), 2010, pp. 125-128.
    • [27] X. Wang, B. Cheng, A. R. Brown, C. Millar and A. Asenov, "Accurate Simulations of the Interplay Between Process and Statistical Variability for nanoscale FinFET-based SRAM Cell Stability," in Proc. 44th European Solid-State Device Research Conference (ESSDERC), Venice Italy, Sept. 2014, pp. 349-352.
    • [28] J. Deng, et al., “SOI FinFET nFET-to-pFET Tracking Variability Compact Modeling and Impact on Latch Timing,” IEEE Trans. Electron Devices, vol.62 no.6, pp.1760-1768, June 2015.
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