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Khan, Z-U-A.; Benaissa, M. (2015)
Publisher: Institute of Electrical and Electronics Engineers
Languages: English
Types: Article
Subjects:

Classified by OpenAIRE into

ACM Ref: Hardware_ARITHMETICANDLOGICSTRUCTURES
High throughput while maintaining low resource is a key issue for elliptic curve cryptography (ECC) hardware implementations in many applications. In this brief, an ECC processor architecture over Galois fields is presented, which achieves the best reported throughput/area performance on field-programmable gate array (FPGA) to date. A novel segmented pipelining digit serial multiplier is developed to speed up ECC point multiplication. To achieve low latency, a new combined algorithm is developed for point addition and point doubling with careful scheduling. A compact and flexible distributed-RAM-based memory unit design is developed to increase speed while keeping area low. Further optimizations were made via timing constraints and logic level modifications at the implementation level. The proposed architecture is implemented on Virtex4 (V4), Virtex5 (V5), and Virtex7 (V7) FPGA technologies and, respectively, achieved throughout/slice figures of 19.65, 65.30, and 64.48 (106/(Seconds × Slices)).
  • The results below are discovered through our pilot algorithms. Let us know how we are doing!

    • Mar. 2000. [2] R. Hankerson, A. Menezes, and S. Vanstone, Guide to Elliptic Curve
    • Cryptography. New York: Springer-Verlag, 2004. GF(2m) Without Precomputation, in Proc. 1st Int. Workshop
    • Cryptograph. Hardw. Embedded Syst., 1999, pp. 316-327. [4] 2m)
    • multiplier for curve based cryptography, IEEE Trans. Comput., vol. 55,
    • no. 10, pp. 1306-1311, Oct. 2006. [5] Z. Khan and M. Benaissa, "Low area ECC implementation on FPGA," in
    • Proc. IEEE 20th ICECS, Dec. 8-11, 2013, pp.581-584. [6] T. Itoh and S. Tsujii, A fast algorithm for computing multiplicative
    • inverses in GF (2m J. Inf. Comput., vol. 78, no. 3,
    • pp171-177, 1988. [7] B. Ansari, M. Hasan, High-Performance Architecture of Elliptic Curve
    • Scalar Multiplication, IEEE Trans. Computers, vol.57, no. 11, pp. 1443-
    • 1453, Nov. 2008. [8] S. Roy, C. Rebeiro, and D. Mukhopadhyay,
    • IEEE Trans. VLSI Syst., vol. 21, no. 5, pp. 901 909, May. 2013. [9] W. Chelton and M. Elliptic Curve Cryptography on
    • IEEE Trans. VLSI Syst., vol. 16, no. 2, pp. 198 205, Feb. 2008.
    • Ind. Electron., vol. 60, no. 1, pp. 217-225, 2013. [11] Y. Zhang, D. Chen, Y. Choi, L. Chen and S. -
    • GF(2163 Microprocessors and Microsystems, vol. 34, no. 6, pp. 228
    • 236, Oct. 2010. [12] H. M. Choi, C. P. Hong and C. H. Kim
    • Cryptographic Processor Over GF(2163) in proc. 4th IEEE Intl. Symp. on
    • Electronic Design, Test & Applications, DELTA, 2008, pp. 290 295. [13] H. Mahdizadeh, and M. Masoumi, Novel Architecture for Efficient
    • Over GF(2163), IEEE Trans. VLSI Systems, vol. 21, no. 12, pp. 2330-
    • 2333, Dec. 2013. [14] R. Azarderakhsh and A. Reyhani-
    • VLSI Systems, vol. 20, no. 8, pp. 1453-1466, Aug. 2012. [15] J.-S. Pan, R Azarderakhsh, M. M. Kermani, C.-Y Lee, W.-Y. Lee, C. W.
    • Multiplier Over GF(2m) Using Subquadratic Toeplitz Matrix-Vector
    • Product Approach," IEEE Trans. on Comput., Vol. 63, no. 5, pp.1169-
    • 1181, 2014. [16] C.-Y. Lee, C.-S. Yang, B. K. Meher, P. K. Meher, and J.-S. Pan, "Low-
    • Binary Extension Fields using (b,2)-Way Karatsuba
    • Decomposition," IEEE Trans. Circuits and Syst.-I, vol.. 61, no. 11, pp.
    • 3115 - 3124, 2014. [17] C.-Y. Lee, "Super Digit-Serial Systolic Multiplier over GF(2m)," The
    • Sixth ICGEC., Aug.25-28, 2012, pp. 509-513.
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