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Yang, L.; Watling, J.R.; Wilkins, R.C.W.; Asenov, A.; Barker, J.R.; Roy, S.; Hackbarth, T. (2002)
Publisher: Institute of Electrical and Electronics Engineers
Languages: English
Types: Other
Subjects: TK

Classified by OpenAIRE into

ACM Ref: Hardware_PERFORMANCEANDRELIABILITY, Hardware_INTEGRATEDCIRCUITS
Based on the successful calibration on a 0.25 /spl mu/m strained Si/SiGe n-type MODFET, this paper presents a gate length scaling study of double-side doped Si/SiGe MODFETs. Our simulations show that gate length scaling improves device RF performance. However, the short channel effects (SCE) along with the parasitic delays limit the device performance improvements. We find that it is necessary to consider scaling (dimensions and doping) of both the lateral and vertical architecture in order to optimize the device design.

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