LOGIN TO YOUR ACCOUNT

Username
Password
Remember Me
Or use your Academic/Social account:

CREATE AN ACCOUNT

Or use your Academic/Social account:

Congratulations!

You have just completed your registration at OpenAire.

Before you can login to the site, you will need to activate your account. An e-mail will be sent to you with the proper instructions.

Important!

Please note that this site is currently undergoing Beta testing.
Any new content you create is not guaranteed to be present to the final version of the site upon release.

Thank you for your patience,
OpenAire Dev Team.

Close This Message

CREATE AN ACCOUNT

Name:
Username:
Password:
Verify Password:
E-mail:
Verify E-mail:
*All Fields Are Required.
Please Verify You Are Human:
fbtwitterlinkedinvimeoflicker grey 14rssslideshare1
Chalamalasetti, S.R.; Purohit, S.; Margala, M.; Vanderbauwhede, W. (2009)
Publisher: IEEE Computer Society
Languages: English
Types: Part of book or chapter of book
Subjects: QA75

Classified by OpenAIRE into

ACM Ref: ComputingMethodologies_SYMBOLICANDALGEBRAICMANIPULATION
This paper presents an architecture and implementation details for MORA, a novel coarse grained reconfigurable processor for accelerating media processing applications. The MORA architecture involves a 2-D array of several such processors, to deliver low cost, high throughput performance in media processing applications. A distinguishing feature of the MORA architecture is the co-design of hardware architecture and low-level programming language throughout the design cycle. The implementation details for the single MORA processor, and benchmark evaluation using a cycle accurate simulator are presented.
  • The results below are discovered through our pilot algorithms. Let us know how we are doing!

    • [1] E. Mirsky and A. DeHon, “MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources,” in Proc. IEEE Symposium on FPGAs for Custom Computing Machines, pp. 157-166, 1996.
    • [2] M. Cocco, J. Dielissen, M. Heijligers, A. Hekstra,J. Huisken, S. Hive, and N. Eindhoven, “A scalable architecture for LDPC decoding,” in Proceedings of Design, Automation and Test in Europe Conference and Exhibition, vol.3,pp- 88-93, 2004.
    • [3] Mike Butts, "Synchronization through Communication in a Massively Parallel Processor Array," IEEE Micro, vol. 27, no. 5, pp. 32-40, September/October, 2007.
    • [4] Z. Yu, M. Meeuwsen, R. Apperson, O. Sattari, M. Lai, J. Webb, E. Work, D. Truong, T. Mohsenin, B. Baas, "AsAP: An Asynchronous Array of Simple Processors,"IEEE Journal of Solid-State Circuits (JSSC), vol. 43, no. 3, pp. 695-705, 2008.
    • [5] DAPDNA-2 Dynamically Reconfigurable Processor product brochure, IPFlex Inc., 13th March 2007. http://www.ipflex.com/en/E1-products/dd2Arch.html.
    • [6] S. Purohit, S. Chalamalasetti, M. Margala, P. Corsonello,"Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices," in Proceedings of International Conference on Reconfigurable Computing and FPGAs, pp. 217-222, 2008.
    • [7] S. Krithivasan, M.J Schulte, "Multiplier architectures for media processing," Record of the 37th Asilomar Conference on Signals, Systems and Computers, pp. 2193-2197, 2003.
    • [8] M. Lanuzza, S. Perri, P. Corsonello, M. Margala, "A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications," 2nd NASA/ESA Conference on Adaptive Hardware and Systems, pp-119-126, 2007.
    • [9] A. Karandikar, K.K Parhi, "Low power SRAM design using hierarchical divided bit-line approach ," Proceedings of International Conference on Computer Design, pp. 82-88, 1998.
    • [10] M. Lanuzza, S. Perri, P. Corsonello,” MORA- A New Coarse Grain Reconfigurable Array for High Throughput Multimedia Processing”, Proceedings of International Symposium on Systems, Architecture, Modeling and Simulation,( SAMOS), pp-159-168, 2007.
  • No related research data.
  • No similar publications.

Share - Bookmark

Cite this article