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Wang, Yijiao; Al-Ameri, Talib; Wang, Xingsheng; Georgiev, Vihar P.; Towie, Ewan; Amoroso, Salvatore Maria; Brown, Andrew R.; Cheng, Binjie; Reid, David; Riddet, Craig; Shifren, Lucian; Sinha, Saurabh; Yeric, Greg; Aitken, Robert; Liu, Xiaoyan; Kang, Jinfeng; Asenov, Asen (2015)
Publisher: IEEE
Languages: English
Types: Article
Subjects:

Classified by OpenAIRE into

arxiv: Computer Science::Hardware Architecture, Computer Science::Emerging Technologies
In this paper, we have studied the impact of quantum confinement on the performance of n-type silicon nanowire transistors (NWTs) for application in advanced CMOS technologies. The 3-D drift-diffusion simulations based on the density gradient approach that has been calibrated with respect to the solution of the Schrödinger equation in 2-D cross sections along the direction of the transport are presented. The simulated NWTs have cross sections and dimensional characteristics representative of the transistors expected at a 7-nm CMOS technology. Different gate lengths, cross-sectional shapes, spacer thicknesses, and doping steepness were considered. We have studied the impact of the quantum corrections on the gate capacitance, mobile charge in the channel, drain-induced barrier lowering, and subthreshold slope. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also investigated. We have also estimated the optimal gate length for different NWT design conditions.
  • The results below are discovered through our pilot algorithms. Let us know how we are doing!

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    • Yijiao Wang received the B.S. degree in microelectronics from Xidian University, Xi'an, China, in 2011. She is currently pursuing the Ph.D. degree with the Institute of Microelectronics, Peking University, Beijing, China. She is an Honorary Research Associate with the Device Modelling Group, School of Engineering, University of Glasgow, Glasgow, U.K.
    • Talib Al-Ameri received the B.Sc. and M.Sc. degrees from the University of Technology at Baghdad, Baghdad, Iraq, in 1998 and 2004, respectively. He is currently pursuing the Ph.D. degree with the Device Modelling Group, School of Engineering, University of Glasgow, Glasgow, U.K. He has been a Lecturer with the Department of Electronics and Electrical Engineering, Al-Mustansiriya University, Baghdad, since 2005.
    • Xingsheng Wang (M'11) received the master's degree in mathematics from Tsinghua University, Beijing, China, in 2007, and the Ph.D. degree in electronics and electrical engineering from the University of Glasgow, Glasgow, U.K., in 2010. He is currently with the School of Engineering, University of Glasgow. His current research interests include nanoscale transistors, statistical variability and reliability, and device circuit co-design.
    • Vihar P. Georgiev received the Ph.D. degree from the University of Oxford, Oxford, U.K., in 2011. He joined the Device Modelling Group, School of Engineering, University of Glasgow, Glasgow, U.K., in 2011, where he was a Research Associate until 2015. He is currently a Lecturer in Electronics and Nanoscale Engineering with the School of Engineering, University of Glasgow.
    • Ewan Towie received the B.Eng. degree in electronics and software engineering and the Ph.D. degree from the University of Glasgow, Glasgow, U.K., in 2004 and 2009, respectively. He was a member of the Device Modelling Group with the School of Engineering, University of Glasgow, from 2009 to 2013. He is currently a Chief Developer with Gold Standard Simulations Ltd., Glasgow.
    • Salvatore Maria Amoroso (S'10-M'12) received the Ph.D. degree in electronics engineering from the Politecnico di Milano, Milan, Italy, in 2012. He was an Associate Researcher with the Department of Electronics, University of Glasgow, Glasgow, U.K., from 2012 to 2014. He is currently a Chief Developer with Gold Standard Simulations Ltd., Glasgow.
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