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Ma, J; Zhang, WD; Zhang, JF; Ji, Z; Benbakhti, B; Franco, J; Mitard, J; Witters, L; Collaert, N; Groeseneken, G
Publisher: IEEE
Languages: English
Types: Unknown
Subjects: TA
For the first time, AC lifetime in Si-cap/Ge and GeO2/Ge pMOSFETs is investigated and it must not be predicted by the conventional DC stress method with a measurement delay. This is because the energy alternating defects are generated in Ge devices but not in Si, which introduces additional generation under DC stress.
  • The results below are discovered through our pilot algorithms. Let us know how we are doing!

    • 0.10 1)V0-1 ( h 1E3o.x5_MopV/cm 1Δt-V0-2 (AECffesctrteivses tsLU)infedFDtreuiemtrqy-eeF=sa1tc0itkmoHra=z5ti0o%n 5 10 15 20 25 100 101 102 103 |Eox| (MV/cm) Effective stress tim e (s)
    • Fig.2 For Ge devices, AC Fig.3 In contrast to Si in Fig.1c, Si-
    • underestimated by 0.5V. a delay in the order of seconds. 0.12 0.5
    • 0.4 DC stress Si-cap Ge Fig.8 An illustration of energy alternating defects (EAD) in (a) GeO2/Ge and (b) Si-Cap/Ge: their energy level shifts above Ev when charged and back below Ev when neutralized. (c) In SiON, defect energy does not alternate with charge status and recharge takes place by e-tunnelling back to Si conduction band.
    • Δt/t()(r)ch_heVAVDCC00001.....68420 (iETSESnaorLomqcGi)aloxuripdnewaet:ygrOa:eElesEE2:o:ehoo/xlGoiSRgweh:EEDIooCmxxHpaigDEAafhtucAdeEttdrDyooirxtFeGfoacEencoonatvoxleerrDra=yCti5o0n% Δ210123trc_heVDCt/()hAC()......055050 (SEboml)iDpdt:Cy: EEaooftSRSeInirTOSdrrqDiNeeaupCnc/aSgeorlebinev:e:dehlfroeiogywnrhteRDEEooeeroxeffcxecEoD=covou5tvexts0yer%Faraybcltoer VVggsstt,,12vpEslno.ettrtheg1adysttrilNweenvvehFeelirllgsie.s8ly tim2end well DACC
    • FΔ0.i10g0.-121D10C-1A10FC0re1q0Nu1e1Bn0cT2y1I0(H3vz1s)0.4 1f0r5e1q0u6enΔ0Vc.y100-n21Do0rC-m11a0Fl0riez1qe0ud1e1n0bc2yy10(HD3z1C)04 1a0ft5e1r06 gFeign.e9ratiDoonubloef-weelnlermgyodeallteirnnatGineg:
    • recovery. (a) In Ge, the additional EAD generation starts at defects in 2nd well with deeper energy
    • higher frequency under higher Eox. (b) In Si devices, the level requires holes in 1st well to
    • difference between AC and DC is caused by discharging overcome the 2nd barrier, through a
    • recoverable defects only, independent of Eox. field-enhance relaxation process. −Δ0t()hVVF.0i0.g111.11SaD(0f3aCtt0er)1resI0trnsre1esc1sGo0stv2iee1mry0de3 1e(0vs4i)1c0Ee5,f1feAt(0hbcC01te)isv0trDe1e1ss0Cst2r1eG----N02110se....37949s1OB5MMMM02tVVVTVi/4///m1G/ccccmmmIm0ee5a(fst)er 1τiliitffft,()vcseeeeEm11111100F000001-0220468ig(r1aDGbe2.feC)1t0E5ceO.oC42osrx20vt_/GAreMo0Ee.pero|V4CsyEAx/3sc_o1CMmolxpiV|sf/(tecMrmte9EiVs.Smo8/1EsixcOM0_oe1Em.oNx3V1op_S./c)/x5SMcoi_a-imp1MocVn0pa/Vcnp/mc/oGmtebecab))) 22p4.nnSSGTr3mmeiinae-OdcmHbOAaNilf2ecpolO//2SGt/r1OGe2i2:/e3d~eG/n10ma..b24tynnepmmslDtaSasicmCOka2/-N recovery (a) is substantially higher than with recovery at Vg_rec=0V for Ge devices, the AC NBTI (10 kHz), due to the whilst it can for Si devices since its AC and DC 'additional DC generation' (Fig. 5) (with recovery) overlapped.
  • No related research data.
  • Discovered through pilot similarity algorithms. Send us your feedback.

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