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Djellid-Ouar , Anissa; Cathébras , Guy; Bancel , Frédéric (2006)
Publisher: HAL CCSD
Languages: English
Types: Conference object
Subjects: [ SPI.NANO ] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, [ SPI.OTHER ] Engineering Sciences [physics]/Other

Classified by OpenAIRE into

ACM Ref: Hardware_PERFORMANCEANDRELIABILITY, Hardware_LOGICDESIGN, Hardware_INTEGRATEDCIRCUITS
International audience; Among the attacks applied on secure circuits, fault injection techniques consist in the use of a combination of environmental conditions that induce computational errors in the chip that can leak protected informations. The purpose of our study is to build an accurate model able to describe the behaviour of CMOS circuits in presence of deliberated short supply voltage variations. This behaviour depends strongly on the basic gates (combinational logic, registers. . . ) that make up the circuit. In this paper, we show why D-flip-flop are resistant to power supply glitches occurring between clock transitions and we propose an approach to evaluate the basic elements sensitivities towards faults generated by power glitches. Our aimed model will consequently be dependent on this sensitivity.
  • The results below are discovered through our pilot algorithms. Let us know how we are doing!

    • [1] D. Boneh, R. A. DeMillo, and R. J. Lipton, “On the importance of checking cryptographic protocols for faults,” in Proc. Advances in Cryptology - EUROCRYPT '97: International Conference on the Theory and Application of Cryptographic Techniques, ser. Lecture Notes in Computer Science, vol. 1233. Konstanz, Germany: Springer-Verlag, May 1997, pp. 37-51.
    • [2] H. Bar-El, H. Choukri, D. Naccache, M. Tunstall, and C. Whelan, “The sorcerer's apprentice guide to fault attacks,” Proceedings of the IEEE, vol. 94, no. 2, pp. 370-382, Feb. 2006.
    • [3] R. J. Anderson and M. G. Kuhn, “Low cost attacks on tamper resistant devices,” in Proc. 5th International Workshop on Security Protocols, ser. Lecture Notes in Computer Science, vol. 1361. Paris, France: SpringerVerlag, Apr. 7-9, 1997, pp. 125-136.
    • [4] S. Skorobogatov and R. Anderson, “Optical fault induction attacks,” in Proc. Cryptographic Hardware and Embedded Systems - CHES 2002: 4th International Workshop, ser. Lecture Notes in Computer Science, vol. 2523. Redwood Shores, CA, USA: Springer-Verlag, Aug. 13-15, 2002, pp. 2-12.
    • [5] J.-M. Dutertre, “Circuits reconfigurables robustes,” thèse de doctorat, Université de Montpellier 2, oct 2002.
    • [6] T. Monnier, “Durcissement de circuits convertisseurs a/n rapides fonctionnant en environnement spatial,” thèse de doctorat, Université de Montpellier 2, oct 1999.
    • [7] D. Leroy, S. J. Piestrak, F. Monteiro, and A. Dandache, “Modeling of transients caused by a laser attack on smart cards,” in Proc. IOLTS 2005, 11th IEEE International On-Line Testing Symposium , 2005, pp. 193-194.
    • [8] L. Anghel, “Test des circuits intégrés, cours de l'école d'électronique numérique IN2P3 ENSERG-INP Grenoble,” 2003, unpublished.
  • No related research data.
  • No similar publications.

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